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features access time : 55 ns low power consumption: operatingcurrent : 30 ma (typ.) standby current : 4 a (typ.) single 2.7v ~ 5.5v power supply all outputs ttl compatible fully static operation tri-state output data retention voltage :1.5v (min.) all products rohs complia nt general description the as6c4008 is a 4,194,304-bit low power cm os static random access memory organized as 524,288 words by 8 bits. it is fabricated using very high performance, high reliability cm os technology. its standby current is stable wi th in the range of operating temperature. the as6c4008 is well designed for very low power system applications, and particularly well suited for battery back-up non-volatile memory application. th e a s6c4008 operates from a single power supply of 2.7v~ 5.5vand all inputs and outputs are fully ttl compatible functional block diagram decoder i/o data circuit control circuit 51 2kx8 memory array column i/o a0-a18 vcc vss dq0-dq7 ce# we# oe# pin description** august 2009 512k x 8 bit low power cmos sram as6c4008 aug/09, v 1.4 alliance memory inc package : 32-pin 450 mil sop ;32-pin 600 mil p-dip 32-pin 8mm x 20mm tsop-i 32-pin 8mm x 13.4mm stsop 36-ball 6mm x 8mm tfbga 32-pin 400 mil tsop-ii symbol description a0 - a18 address inputs dq0 C dq7 data inputs/outputs ce# chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection product family power dissipation product family operating temperature vcc range speed standby(i sb1 typ.) operating(icc,typ.) as6c4008 -40 ~ +85 2.7 ~ 5.5v 55ns 4a(ll) 30ma p age 1 o f 14
pin configuration august 2009 512k x 8 bit low power cmos sram as6c4008 aug/09, v 1.4 alliance memory inc page 2 of 14 as6c4008 as6c4008 as6c4008 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss a14 vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 sop / p-dip 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a13 ce# oe# we# a16 a18 29 32 30 31 a17 a15 tsop-i/stsop dq3 a11 a9 a8 a13 dq2 a10 a14 a12 a7 a6 a5 vcc dq7 dq6 dq5 dq4 vss dq1 dq0 a0 a1 a2 a4 a3 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# a17 a15 a16 a18 32 31 29 30 a14 a16 a18 a13 a7 a6 a5 a4 a3 dq3 dq0 a8 a9 a10 a11 oe# ce# tsop-ii 21 10 9 8 7 6 5 4 3 2 1 12 11 15 14 71 61 18 19 20 dq1 a12 a1 a0 vcc a15 dq6 a2 dq2 vss dq5 dq7 25 22 23 24 32 29 30 31 26 27 28 dq4 we# a17 13 tfbga oe# we# a12a11 a13 nc a18 a10 a14 a15 dq5 dq6 dq7 a9 vss a8 a16 dq4 vcc vcc dq3 a17 vss a7 a0 dq2 dq1 dq0 a6 a1 a3 a5nc a4 a2 123 4 5 6 h g c d e f a b ce#
absolute maximum ratings* parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 6.5 v 0 to 70(c grade) t erutarepmetgnitarepo a -40 to 85(i grade) t erutarepmetegarots stg -65 to 150 c p noitapissidrewop d 1 w i tnerructuptuocd out 50 ma soldering temperature (under 10 sec) t solder 260 *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliability. truth table mode ce# oe# we# i/o operation supply current standby h x x high-z i sb1 output disable l h h high-z i cc ,i cc1 read l l h d out i cc ,i cc1 write l x l d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. *3 max. unit supply voltage v cc v5.50.37.2 input high voltage v ih *1 0.7*vcc - v cc +0.3 v input low voltage v il *1 v6.0-2.0- input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh v--4.2 am1-= output low voltage v ol i ol = 2ma - - 0.4 v - 55 - 30 60 ma i cc cycle time = min. ce# = 0.2v, i i/o = 0ma o ther pins at 0.2v or v cc - 0.2v average operating power supply current i cc1 cycle time = 1 s ce# = 0.2v, i i/o = 0ma other pins at 0.2v or v cc - 0.2v - 4 10 ma -ll - 4 50 *4 a standby power supply current i sb1 ce# v R cc - 0.2v -lle/-lli - 4 50 *4 a notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. v il (min) = v ss - 3.0v for pulse width less than 10ns. 2. over/undershoot specifications are characterized, not 100% tested. 3. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 ? 4. 25 a for special request o c o c o $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug/09, v 1.4 alliance memory inc page 3 of 14
cap aci ta nce (t a = 25 , f = 1.0mhz) parameter symbol min. max unit c ecnaticapac tupni in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions v ot v2.0 slevel eslup tupni cc - 0.2v sn3 semit llaf dna esir tupni input and output timing reference levels 1.5v c daol tuptuo l = 30pf + 1ttl, i oh /i ol = -2ma/4ma ac electrical characteristics (1) read cycle as6c4008-55 -55 param eter sym. min. max. unit t emit elcyc daer rc 55 - a dd ress acce ss time t aa - 55 chip enable access time t ace - 55 output enable access time t oe - 30 chip enable to output in low-z t clz * 10 - output enable to output in low-z t olz * 5 - chip disable to output in high-z t chz * - 20 ns ns ns ns ns ns ns ns ns output disable to output in high-z t ohz * - 20 output hold from address change t oh 10 - (2) write cycle as6c4008 min. max. unit t emit elcyc etirw wc 55 - ns ns ns ns ns ns ns ns ns ns address valid to end of write t aw 50 - chip enable to end of write t cw 50 - address set-up time t as 0 - t htdiw eslup etirw wp 45 - write recovery time t wr 0 - da ta to write t ime overlap t dw 25 - data hold from end of write time t dh 0 output active from end of write t ow * 5 - write to output in high-z t whz * - 20 *these parameters are guaranteed by device characterization, but not production tested. param eter sym. $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 4 of 14
timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc prev iou s data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout da ta va lid t oh oe# t ace ce# t aa address t rc hig h-z high-z t clz t olz t oe t chz t ohz notes : 1.we # is high for read cycle. 2.device is continuous ly selected oe# = lo w, ce# = low . 3.a ddress must be valid prior to or coincident with ce# = low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 5 00 mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz. $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 5 of 14
write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc (4) t ow write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc notes : 1.we #, ce# must be high during all address tr ansitions. 2.a write occurs during the overlap of a low ce#, low we#. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce# low transition occ urs simultaneously with or after we # low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from stead y state. $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 6 of 14
data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 1.5 - 5.5 v -ll - 2 30 a data retention current i dr v cc = 1.5v ce# v R cc - 0.2v -lle/-lli - 2 30 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform vcc ce# v dr R 1.5 v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) $8*867 2009 512k x 8 bit low power cmos sram as6c4008 $8*y alliance memory inc page 7 of 14
package outline dimension 32 pin 450 mil sop package outline dimension unit sym. inch.(base) mm(ref) a 0.118 (max) 2.997 (max) a1 0.004(min) 0.102(min) a2 0.111(max) 2.82(max) b 0.016(typ) 0.406(typ) c 0.008(typ) 0.203(typ) d 0.817(max) 20.75(max) e 0.445 0.005 11.303 0.127 e1 0.555 0.012 14.097 0.305 e 0.050(typ) 1.270(typ) l 0.0347 0.008 0.881 0.203 l1 0.055 0.008 1.397 0.203 s 0. 026 (max) 0.660 (max) y 0.004(max) 0.101(max) 0 o -10 o 0 o -10 o $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 8 of 14
32 pin 8mm x 20mm tsop-i package outline dimension unit sym. inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 + 0. 002 - 0.001 0.20 + 0.05 -0.03 c 0.005 (typ) 0.127 (typ) d 0.724 0.004 18.40 0.10 e 0.315 0.004 8.00 0.10 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.08 0.10 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o $8*867 2009 512k x 8 bit low power cmos sram as6c4008 $8*y alliance memory inc page 9 of 14
32 pin 8mm x 13.4mm stsop package outline dimension 1 16 17 32 c l hd d "a" e e 12 (2x) 12 (2x) s ea ting plane y 32 17 16 1 c a2 a1 l a 0.254 0 gauge pl ane 12 (2x) 12 (2x) s eat ing pl ane "a" detail vi ew l1 b unit sym. inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.005 0.002 0.130 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 0.01 0.20 0.025 c 0.005 (typ) 0.127 (typ) d 0.465 0.004 11.80 0.10 e 0.315 0.004 8.00 0.10 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.8 0.10 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o $8*867 2009 512k x 8 bit low power cmos sram as6c4008 $8*y alliance memory inc page 10 of 14
36 ball 6mm 8mm tfbga package outline dimension $8*867 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 11 of 14
32-pin 400mil tsop- package outline dimension august 2009 512k x 8 bit low power cmos sram as6c4008 aug/09, v 1.0.a alliance memory inc page 12 of 14
august 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc pa ge 13 of 14 32 pin 600 mil p-dip package outline dimension 32 pin 600 m il p-dip package outline dimension note : d/e1/s dimension do not include mold flash. unit sym. inch(base) mm(ref) a1 0.001 (min) 0.254 (min) a2 0.150 0.005 3.810 0.127 b 0.018 0.005 0.457 0.127 d 1.650 0.005 41.910 0.127 e 0.600 0.010 15.240 0.254 e1 0.544 0.004 13.818 0.102 e 0.100 (typ) 2.540 (typ) eb 0.640 0.020 16.256 0.508. l 0.130 0.010 3.302 0.254 s 0.075 0.010 1.905 0.254 q1 0.070 0.005 1.778 0.127
august 2009 512k x 8 bit low power cmos sram as6c4008 aug09 v1.4 alliance memory inc page 14 of 14 ordering part numbering system information alliance organization vcc package operating temp speed ns as6c4008-55pcn 512k x 8 5v 32pin 600mil dip comm ercial ~ 0o c to 70o c 55 as6c4008 -55sin 512k x 8 5v 32 pin 450mil sop industrial ~ -40oc to 85o c 55 as6c4008-55tin 512k x 8 5v 32 pin tsop 1 (8 x 20 mm) industrial ~ -40oc to 85o c 55 as6c4008-55stin 512k x 8 5v 32 pin stsop (8 x 13.4 mm) industrial ~ -40oc to 85o c 55 as6c4008-55bin 512k x 512k x 8 8 5v 36pin tfbga (6mm x 8mm) industrial ~ -40oc to 85o c industrial ~ -40oc to 85o c 55 55 as6c4008-55zin 5v 32-pin 400mil tsop 11 as6c 4008 - 55 x x n temperature range: c = commercial (0oc to +70o c) i = industrial (-40o to +85o c) n = lead free rohs compliant part low power sram prefix device number 40 = 4m 08 = by 8 access time package options: p = 32 pin 600 mil p-dip s = 32 pin 450 mil sop t = z = 32-pin 400mil tsop 11 32 pin tsop 1 (8mm x 20 mm) st = 32 pin stsop (8mm x 13.4 mm) b = 36 pin tfbga (6mm x 8mm)

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